Marin Ivezic
Two decks arrive in the same week. One company reports 256 qubits, the other 36. On the headline number the first looks seven times ahead, and on every measurement that decides whether either machine can finish a useful circuit, the comparison hasn’t started.
Qubit count is the only hardware specification that survives translation into a slide without losing anything, which is why it’s the number that gets translated. The properties that actually constrain a quantum processor take a paragraph and a chart each: how long the qubits hold their state, how often each operation goes wrong, how those errors compound over a circuit, and whether the second device off the line behaves like the first.
This article covers the technical half of company evaluation. It walks through what the standard metrics mean, how they interact, what each hardware approach can plausibly be pushed toward, and what separates a laboratory result from something a factory can produce. Business model, funding position, and market timing are separate questions with separate evidence, and folding them into a technical review usually buries the technical answer.
Reading the Spec Sheet
Four figures appear on almost every quantum hardware slide. Each is easy to quote and easy to quote badly.
Coherence Time
A qubit holds quantum information only while it stays isolated from its surroundings. Coherence time measures how long that lasts. Two numbers are usually reported. T1 is the energy relaxation time, the interval over which a qubit in its excited state decays back to its ground state. T2 is the dephasing time, which tracks how long the qubit keeps a well-defined phase relationship, and phase is what superposition and entanglement are built from. T2 is the harder number to hold up and the more useful one.
The figure alone tells you very little without three qualifiers. Was it measured on an idle qubit in isolation, or on a qubit inside a running circuit with its neighbours active? Was it the best qubit on the chip or the median across all of them? And how does it compare to the time a single operation takes on that machine?
That last ratio is where coherence becomes meaningful. A superconducting processor with a T2 near 100 microseconds and two-qubit gates around 60 nanoseconds has room for well over a thousand gate durations before the state decays. Coherence isn’t what stops that machine. Gate error is.
Gate Fidelity
Fidelity is the accuracy of an operation, expressed as one minus its error rate. A gate quoted at 99.5% fails roughly once every two hundred times it runs.
Errors compound multiplicatively, so a small change in the per-gate figure produces a large change in what the machine can execute. Run 200 two-qubit gates at 99.5% fidelity and roughly 37% of runs come through clean. Raise the gate to 99.9% and that rises to about 82%. The same 200-gate circuit is either marginal or comfortable depending on a difference of four tenths of a percentage point.
Four questions turn a fidelity number into information. Is it single-qubit or two-qubit fidelity? Two-qubit entangling gates are consistently worse and are almost always the binding constraint, so a slide showing only the single-qubit figure has told you the easy half. Is it median or best-case, and what is the spread across the device? Was it measured on an isolated pair, or with the rest of the chip operating simultaneously? Crosstalk between neighbouring qubits degrades performance considerably, and isolated-pair numbers systematically flatter a device. And how was it measured? Randomized benchmarking, where the machine runs long random sequences of gates that should compose back to the identity operation and the output degradation is fitted against sequence length, is the standard method and it has a published methodology you can check.
IBM’s layer fidelity metric exists specifically because isolated-pair measurements were overstating whole-device performance. A company reporting simultaneous-operation figures is telling you something the isolated numbers hide.
Physical and Logical Qubits
A physical qubit is the hardware object: a superconducting circuit, a trapped ion, an atom in an optical tweezer. Every physical qubit currently in existence is noisy at rates far above what long algorithms need.
A logical qubit is an error-corrected qubit built from many physical qubits. Quantum error correction (QEC) spreads one unit of quantum information across a block of physical qubits and repeatedly measures parity relationships between them. Those measurements reveal that an error occurred and where, without reading out the encoded information itself, which would destroy it. The surface code is the leading approach. Its code distance, written as d, sets how many simultaneous errors the block can survive, and a rotated surface code of distance d consumes roughly 2d² minus one physical qubits. Distance 7 comes to 97.
Two thresholds matter. First, physical error rates have to drop below a critical value before adding more physical qubits reduces the logical error rate rather than increasing it. Under idealised noise models that threshold sits near 1%, and the practical engineering target is closer to one error in a thousand, because the overhead at 1% is ruinous. Google’s 2024 Nature result ran a distance-7 surface code on a 105-qubit processor and reported the logical error rate roughly halving each time the code distance rose by two, which is the behaviour the theory predicts on the correct side of threshold.
Second, the overhead is enormous and it moves. Craig Gidney and Martin Ekerå estimated in 2019 that factoring RSA-2048 would take roughly 20 million physical qubits running for eight hours. Gidney’s 2025 revision put it under a million qubits, a reduction driven by better algorithms and better codes rather than better hardware. Anyone quoting a fixed physical-to-logical ratio is quoting a moving number.
The practical consequence for reading a deck is short. If a company says “qubits” without a qualifier, assume physical, and ask what the logical error rate is and whether it has been measured below the physical error rate of the constituent qubits. That crossing is the milestone. Everything before it is preparation.
Benchmarks That Aggregate
Single metrics can be gamed by optimising the one thing being measured, which is why aggregate benchmarks exist. Quantum Volume, introduced by IBM, is the most widely reported. It runs square random circuits of equal width and depth and returns the largest size the machine can execute while still producing correct outputs above a statistical bar. It compresses qubit count, fidelity, and connectivity into one figure, and it has real limits: it requires classical simulation to verify, so it stops being practical to validate at sizes beyond what classical resources can feasibly simulate, and its square-circuit shape doesn’t resemble most real algorithms.
Vendor-defined composites deserve more caution. When a company reports performance in units it invented and controls, the reasonable question is why the standard benchmarks weren’t used instead. The QED-C application-oriented benchmark suite is a useful counterweight, since it measures machines on algorithm-shaped workloads with a published, community-reviewed methodology.
The Modality Sets the Ceiling
A modality is the physical system a company has chosen to make qubits out of. The choice is close to irreversible, because it determines the fabrication process, the control hardware, the cooling requirements, and the engineering team’s skill mix. It also determines which questions are worth asking. Coherence time is a live concern for superconducting hardware and nearly irrelevant for trapped ions. Wiring density is a superconducting problem and a non-problem for photonics.
Superconducting circuits are used by IBM, Google, and Rigetti. Gates are fast, in the tens to hundreds of nanoseconds, and the chips are made lithographically on wafers, which is a genuine manufacturing advantage. The constraints are cooling and wiring. Every chip needs a dilution refrigerator holding roughly 10 to 15 millikelvin, and every qubit needs control and readout lines running into that refrigerator. A thousand-qubit device with one coaxial cable per qubit doesn’t fit in the fridge. Ask what the wiring plan is past the current device, whether control electronics are moving into the cold stage as cryo-CMOS, which puts conventional silicon control chips inside the refrigerator, and what fraction of fabricated chips meet specification.
Trapped ions are used by IonQ and Quantinuum. Every ion of a given species is identical, coherence runs from seconds to minutes, connectivity within a trap is all-to-all, and the highest reported gate fidelities in the field come from this approach. The cost is clock speed: two-qubit gates take tens to hundreds of microseconds, which is roughly a thousand times slower than superconducting gates. A trapped-ion machine with better fidelity can still lose on total time to solution. Ask for gate duration alongside fidelity, and ask what happens past a single trap, since scaling requires either photonic links between traps or QCCD architectures, short for quantum charge-coupled device, which physically shuttle ions between processing zones.
Neutral atoms are used by QuEra, Pasqal, and Atom Computing. Atoms are held in arrays of optical tweezers, and the arrays grow by adding laser power and optics rather than by adding wiring, so site counts have risen quickly. Connectivity is reconfigurable, because the tweezers can move atoms during a computation, and Dolev Bluvstein and colleagues used that property in a 2023 Nature paper to operate 48 logical qubits. The constraints are atom loss and cycle time. Atoms escape the traps and the array has to be reloaded, so ask about repetition rate, loss per cycle, and whether mid-circuit measurement works without disturbing neighbouring atoms.
Photonics is used by PsiQuantum and Xanadu. Photons barely interact with their environment, the chips can be made in existing silicon photonics fabrication lines, and the manufacturing story is the strongest in the field. The constraints are loss and detection. Single-photon sources are probabilistic, every optical component loses photons, and the superconducting nanowire detectors that read the output run at a few kelvin. A photonic system described as room-temperature is usually room-temperature everywhere except the detectors, so the useful question is what the entire system requires, not what the processor chip requires.
Silicon spin qubits are used by Intel, Diraq, and Quantum Motion. Qubits are individual electron spins in silicon devices, they are physically tiny, and they can be produced on standard 300 mm CMOS lines, which is the closest thing in quantum hardware to an existing high-volume process. The constraint is uniformity. Small variations between nominally identical devices shift each qubit’s operating frequency, and qubit counts remain far behind the other approaches. Ask about device-to-device variability and about the calibration cost of a large array.
From One Device to a Product Line
Semiconductor manufacturing spent decades turning yield, the fraction of fabricated devices that meet specification, into its central operating number. Quantum hardware is at the stage where yield is often not reported at all. Two questions close most of that gap.
Reproducibility
A result achieved once, by the group that built the apparatus, under conditions they tuned for weeks, is a scientific result. It’s not yet an engineering capability. The evidence that distinguishes them is boring and specific: run-to-run variance on the same circuit, how often the machine needs recalibration and how long calibration takes, measured uptime over a quarter, and performance data from a second device built to the same design.
Cloud access is the strongest form of this evidence, because it puts the machine in front of users who have no reason to be gentle with it. A company whose device has been open to outside users for a year, with published performance figures over that period, has answered the reproducibility question in a way no slide can.
Manufacturability
Manufacturability is about whether the design can be produced at quantity outside the lab that invented it. Three things are worth checking.
Process standardness. A design that runs on commercial fabrication lines, standard packaging, and off-the-shelf optical or microwave components can scale with demand. A design requiring a process available in two laboratories worldwide has a hard ceiling regardless of how well it performs.
Supply concentration. Dilution refrigerators come from a small number of suppliers, principally Bluefors and Oxford Instruments, with lead times measured in many months. Helium-3, specialist lasers, and low-loss optical fibre have their own bottlenecks. Ask which single-source components sit on the critical path and what the qualified alternative is.
Cost per qubit at the control layer. Room-temperature control electronics currently cost real money per qubit, and that cost scales linearly while the qubit count is meant to scale exponentially. A company with no plan for multiplexing or integrated control has a cost curve that eventually stops the roadmap.
A Worked Assessment
Take a composite specification of the kind that shows up regularly: 64 superconducting qubits, median two-qubit fidelity of 99.4%, median T2 of 90 microseconds, two-qubit gate duration of 60 nanoseconds.
| Question | What the numbers give |
|---|---|
| What circuit depth is reachable? | At 99.4%, errors accumulate to roughly one expected failure after about 166 two-qubit gates. Useful circuits stay in the low hundreds of entangling operations. |
| Is coherence or gate error the constraint? | 90 microseconds divided by 60 nanoseconds is about 1,500 gate durations. Gate error binds first, by a wide margin. |
| Is the device useful for error correction? | A 0.6% error rate sits under the theoretical threshold and above the practical engineering target of roughly one in a thousand. Adding qubits at this rate buys little logical improvement. |
| Could it host a logical qubit? | A distance-7 rotated surface code needs about 97 physical qubits. At 64, the device is under one logical qubit’s worth of hardware. |
None of that makes the company a poor investment. It does mean the roadmap has to answer one question above all others, which is how the two-qubit error rate gets from 0.6% to 0.1%, and whether that path runs through better materials, better control pulses, a different qubit design, or an assumption that hasn’t been tested. Every other line in the deck depends on the answer.
Where the Technical Lens Stops
A technical assessment establishes what the machine currently does and what physics and engineering permit it to do next. It doesn’t establish whether the company can fund the next refrigerator, whether the milestone dates are honest, whether the customer named on slide 14 is paying, or whether a claim was worded to be unfalsifiable. Those are real risks and they need their own evidence. Marin Ivezic’s fuller treatment of the subject on PostQuantum.com covers the commercial and claim-verification dimensions alongside the technical ones.
What the technical lens does do is set the floor. A company whose physics is sound and whose engineering is reproducible can still fail commercially. A company whose two-qubit fidelity has been flat for three years cannot be rescued by a good business plan.
Building the Skill
Reading a quantum hardware deck properly is a learnable skill with a short list of components: the metrics and how they compose, the modalities and their distinct constraints, the error-correction arithmetic, and the manufacturing questions that separate a prototype from a product. Quantum Academy’s certification programs teach these from device data and published results rather than from vendor summaries, and the current catalogue is at quantumacademy.com/.