How to Choose a Quantum Control System

A single-qubit gate on a superconducting transmon is a microwave pulse at 4 to 8 GHz, shaped to roughly 20 nanoseconds, with amplitude and phase calibrated to that one qubit. Something has to generate that pulse. Something has to capture the far weaker signal that comes back when the qubit is read out, decide whether it says zero or one, and act on the answer before the qubit loses its state. That electronics layer is the control system, and it is the reason a quantum processing unit (QPU) computes rather than just sits cold.

We usually find that engineers coming from RF, embedded systems, or test-and-measurement are less surprised by the physics than by the procurement. The instinct from classical infrastructure is that compute arrives quickly and the building takes forever. In a quantum build the cryostat lead time is long but predictable, and the control electronics are the wildcard. We walk the selection decision here in the order an engineer can actually run it: specify first, shortlist second, schedule third.

Write the specification before you open a catalog

Vendor comparison is the last step, not the first. Three numbers determine which systems are even candidates, and all three come from your own machine rather than from anyone’s datasheet.

The latency budget comes from coherence

Every control platform advertises real-time feedback. The number you need is the round trip from measurement to conditional action: measure a qubit, discriminate the result, decide, and emit the next pulse.

Work it backwards from coherence time. T1, the energy relaxation time, is how long a qubit holds an excited state before it decays. A good transmon sits in the low hundreds of microseconds. Quantum error correction (QEC), which detects and repairs errors by measuring extra qubits repeatedly during a circuit, needs many feedback cycles inside that window, so the loop has to close in single-digit microseconds and preferably faster. General-purpose processors can’t guarantee timing that tight, because operating systems introduce jitter. That is why serious platforms run on field-programmable gate arrays (FPGAs), chips whose logic is configured into fixed hardware paths with deterministic timing.

Now run the same calculation for a neutral-atom machine, where atomic coherence can exceed a second. The feedback requirement relaxes by four or five orders of magnitude, and the hard problem moves elsewhere. Two builds, same three functions, completely different specification.

One caution on comparing published latency figures: vendors measure from different points in the chain. Some quote the FPGA decision time, some include digitization, some include the cable run. We ask each vendor for the definition alongside the number, and we get both in writing.

Channel count grows faster than qubit count

Count the physical lines your architecture needs, not the qubits.

A 20-qubit superconducting testbed is a useful worked example. Each qubit needs a drive line for gates. Flux-tunable designs add a flux bias line each for frequency tuning. Readout is the one place you get relief, because 6 to 10 qubits can share a single readout line through frequency multiplexing, with each qubit’s resonator answering at a distinct frequency. Two-qubit gates may need their own drive tones depending on the coupling scheme. So 20 qubits lands somewhere near 40 to 50 analog channels plus 2 to 4 readout chains, and that already exceeds what a single small chassis usually carries.

Two consequences follow. First, arbitrary waveform generators (AWGs) are priced and racked per channel, so channel count drives cost more directly than qubit count does. Second, once you cross a chassis boundary you have a synchronization problem: every module has to share a phase-coherent reference, and drift between racks accumulates across a circuit. We ask how a vendor distributes its clock and what phase stability it holds across a full rack, because that answer is what separates a system that scales from one that merely stacks.

Three purchases that look like one

The industry blurs three layers, and the blur produces muddled specifications.

The control system works at the physical layer, in volts, gigahertz, and nanoseconds. Its job is to execute the lowest-level instructions faithfully.

The orchestration and operating-system layer works above that, handling compilation, job scheduling, calibration management, and hardware abstraction. Some vendors ship a programming environment that reaches into this territory, which is a commercial choice rather than evidence that the layers are the same.

Pulse-optimization firmware sits between the two. Control hardware ships with generic pulse envelopes designed to work adequately across many systems. A pulse shaped for the measured noise profile of one specific chip in one specific cryostat performs better. Q-CTRL’s Boulder Opal is the most visible commercial product here, and the company works with hardware vendors including QuEra to tune pulses against a specific machine’s measured noise.

We would decide all three deliberately. A hardware vendor that solves the first has not necessarily solved the others, and assuming the default pulses are the best your hardware can do leaves fidelity on the table.

The shortlist, by modality

Superconducting and silicon spin

For a superconducting build sourcing components on the open market, we keep the shortlist to four names. Silicon-spin builds, which combine microwave pulses for spin control with low-frequency voltages for tuning the quantum dots, draw from the same shortlist.

Quantum Machines builds its OPX line around a pulse processing unit that synthesizes waveforms in real time from parametric descriptions rather than replaying stored samples from memory. That design supports adaptive sequences without a round trip to a host computer, which is what QEC protocols need. Its QUA language gives pulse-level control without demanding FPGA expertise from the user, and its deployment base is the widest in the field.

Zurich Instruments, part of the Rohde & Schwarz group, takes a test-and-measurement approach: a family of purpose-built instruments tied together by a central synchronizer. The design priority is analog signal quality, and a double-superheterodyne conversion scheme avoids the IQ-mixer calibration work that complicates competing systems. As qubit coherence improves, the electronics rather than the qubit become the fidelity limit, so that advantage compounds. IQM systems default to this platform.

Qblox ships a modular 19-inch rack with swappable drive, readout, and timing modules and a sequence processor on each module. It is the control half of the Quantum Utility Block reference design with QuantWare and Q-CTRL, which pre-validates the QPU-to-control interface, and it has been selected as a manufacture-and-distribute platform for Fermilab’s QICK open-control framework.

Keysight brings RF test-and-measurement heritage and a PXI-based modular system. Its distinguishing strength is the surrounding design tooling, which matters for an organization building from the chip up rather than buying a QPU from a catalog.

Below these four, Tabor Electronics competes on AWG cost, and Berkeley Lab’s QubiC offers an open-source radio-frequency system-on-chip (RFSoC) platform. IBM and Google build their own and don’t sell them.

Whichever wins, we recommend specifying NVQLink compatibility in the purchase. It is NVIDIA’s low-latency link between control electronics and GPUs, and the major vendors have announced support. Real-time decoding will run on that side of the boundary.

Trapped ions: a build-or-buy question

The ion community went the other way. Its de facto standard is open source: ARTIQ, developed by M-Labs with NIST’s ion-storage group, a Python environment that compiles experiment code onto FPGA hardware at nanosecond resolution, paired with the Sinara family of open-hardware boards under the CERN licence.

The reason is technical rather than cultural. Ion control is conditional logic first: which ion to shuttle into which gate zone in a quantum charge-coupled device (QCCD) architecture, which measurement outcome selects the next laser pulse, how to interleave cooling with gates. ARTIQ was designed for that workflow.

So the decision changes shape. ARTIQ gives flexibility and a large community, and it obliges you to keep FPGA and Python capability in house. A commercial stack trades flexibility for supported software. Cost the staffing before you cost the hardware, because on a small team the maintenance burden is the deciding term.

Neutral atoms and photonics

Neutral-atom control is optical. Spatial light modulators and acousto-optic deflectors arrange atoms in tweezer arrays, tuned lasers drive the Rydberg states used for two-qubit gates, and cameras read atomic states by fluorescence. Pasqal’s Pulser, open source under Apache 2.0, is the leading framework. Timing tolerances relax, and the spatial bookkeeping across hundreds of individual atoms gets harder.

Photonic control is optical systems engineering again: photon generation, routing through programmable interferometers, phase stabilization, and classical feed-forward. Photonic companies build this in house.

For both, expect to take the control infrastructure your QPU vendor provides. In our reading of the market, these systems are not yet assembled from independently sourced control components, and treating them as if they were will cost you a quarter.

The line item that moves your schedule

If you act on one section of this guide, make it this one. Every major control platform, and every real-time decoder that runs beside it, depends on FPGAs, often AMD/Xilinx Zynq RFSoC parts, or equivalent platforms such as Intel/Altera devices paired with external data converters. Defense, telecom, and AI hardware buyers want the same silicon, and quantum is a small customer competing against very large ones.

Lead time is therefore often set by FPGA allocation rather than by the vendor’s own build capacity. Three practical steps we would run: pre-qualify the specific FPGA part number and allocation with your control vendor before the purchase order, get the delivery date in writing against that allocation, and if the quoted allocation stretches past about 16 weeks, open a second vendor conversation rather than letting the whole build wait on one queue.

Order control electronics in parallel with the cryostat and the QPU. A program that treats them as a late, low-risk purchase discovers in month four that first qubit signal has moved to month nine.

Budget the integration, not just the boxes

Mixing a QPU from one vendor with control electronics from another works, and it isn’t plug-and-play. No universal protocol exists between a control chassis and a sample holder. Cable runs, trigger timing, reference distribution, and synchronization semantics get negotiated per project.

Published operational reports from multi-vendor deployments describe where the time goes: impedance mismatches found during network-analyzer sweeps after cooldown, unexpected resonances in cable runs, ground loops between rack and fridge that inject low-frequency noise and erode T1. Each fix means another characterize, adjust, and re-cool cycle, and a cooldown is days. None of it is fundamental physics. All of it needs an engineer who understands both sides of the interface, so we put that role in the plan and the budget explicitly.

Buy for a stage, not a destination

Every architecture above puts the electronics at room temperature, connected to millikelvin qubits through a long cable chain that carries heat as well as signal. A transmon drive line stages roughly 60 dB of attenuation across the temperature levels to keep room-temperature thermal noise away from the chip, and a 1,000-qubit machine needs thousands of such connections.

Cryogenic CMOS, meaning conventional silicon logic designed to operate inside the cryostat, is the engineering answer. Intel’s Horse Ridge controllers run at a few kelvin and drive on the order of a hundred qubits over a handful of RF lines using frequency multiplexing. SEEQC takes a different route with single flux quantum logic, a superconducting digital technology that switches on magnetic flux quanta rather than voltage levels.

None of this displaces the room-temperature rack for several years. Silicon spin has a structural head start, since those qubits already tolerate temperatures near 1 K where integration is far easier than at 10 millikelvin. Plan today’s control architecture as a stage in the build, and keep the interface documentation good enough that replacing a layer later is an engineering project rather than an archaeology project.

A selection sequence you can run

1. Derive the feedback latency requirement from your coherence time and your error-correction plan.
2. Count analog channels, including flux and multiplexed readout, and identify the chassis boundary where synchronization becomes a design problem.
3. Separate the three purchases: control hardware, orchestration software, pulse-optimization firmware.
4. Shortlist by modality, not by brand familiarity.
5. Ask every vendor how each published latency figure is defined and measured.
6. Pre-qualify the FPGA allocation in writing before the order.
7. Fund the interface engineering role, in hours, in the project plan.

Where to take this next

Control-system selection sits inside a larger discipline: specifying, sequencing, and integrating the subsystems of a quantum computer from independent suppliers. Our hardware and systems engineering program at Quantum Academy covers that work in depth, including the cryogenic, wiring, and orchestration layers we touch only at their boundaries here. The hardware and systems engineering program page, with current pricing in USD, is at quantumacademy.com/.

For the underlying physics and a deeper vendor-by-vendor technical treatment, Marin Ivezic’s control system build guide on PostQuantum.com goes well past what a selection decision requires.