Marin Ivezic
Ask five security architects which quantum platform will eventually break RSA-2048 and you’ll get five camps: superconducting, trapped ion, neutral atom, photonic, silicon spin. The question assumes a winner. It borrows its shape from the x86 story, in which one instruction set absorbed the market and the alternatives became footnotes. Classical computing then spent three decades unlearning that lesson. A current data center runs CPUs, GPUs, TPUs, FPGAs and DPUs beside one another, each tuned to a narrow class of operations, stitched together by software that routes work to whichever element handles it best.
Quantum computing hasn’t had that reckoning yet. We still see threat assessments tracking a single qubit count on a single processor, and most vendor roadmaps still read as a race. A cryptographically relevant quantum computer, or CRQC – a machine able to break the public-key cryptography now deployed in production – is more likely to be assembled than fabricated. Several qubit technologies, each doing the job it is good at, joined by photonic links and driven by a substantial classical control stack.
We are making an architectural argument, not a hardware forecast. Nobody has built a fault-tolerant quantum processor of any kind at cryptographically relevant scale, and every component described below has unsolved engineering behind it. The architecture still changes how the threat should be monitored.
A QPU is an accelerator, not a computer
A quantum processing unit (QPU) is a coprocessor. It handles a narrow set of mathematical operations faster than a classical processor can, in the same sense that a GPU handles matrix multiplication faster than a CPU does.
Nobody runs a whole application on a GPU, and nobody will run one on a QPU. Shor’s algorithm is a good illustration. The quantum part is modular exponentiation and period finding. The setup, the number theory, the post-processing and the repeated measure-and-retry cycles are all classical. Grover’s algorithm gives a quadratic speedup on one search subroutine, not on the surrounding program.
So every practical quantum computation is already a hybrid. The QPU emits intermediate results that must be decoded and corrected classically, then fed back into the next quantum operation, often within microseconds. The classical control system runs inside the execution loop, decoding and correcting between quantum operations.
Which raises the next question: an accelerator for what, exactly? That’s where the single-chip model comes apart.
No modality is good at everything
Each qubit technology has a distinct profile, and those profiles are not converging. Two properties do most of the sorting. Coherence time is how long a qubit holds its state before noise destroys it. A logical qubit is not one physical qubit. It is many physical qubits encoded together so that errors can be detected and corrected without disturbing the state they hold. The quantum error correction (QEC) cycle is the repeated measure-and-correct step that keeps that encoding alive, and its duration sets the machine’s clock.
| Modality | Strength | Constraint |
|---|---|---|
| Superconducting | Nanosecond gates, QEC cycles near a microsecond, an industrial fabrication base | Millikelvin cryogenics, coherence in the hundreds of microseconds, punishing wiring density at scale |
| Trapped ion | Coherence measured in seconds to minutes, the highest demonstrated two-qubit gate fidelities | Gate times in microseconds to milliseconds, QEC cycles in the tens of milliseconds |
| Neutral atom | Reconfigurable connectivity, large parallel arrays, demonstrated progress toward error-corrected logical operations | Millisecond-scale cycles, atom loss and continuous operation still open |
| Photonic | Room temperature operation, natural fit with telecom fiber | Deterministic generation and manipulation of single photons remains hard |
| Silicon spin | Compatible in principle with CMOS fabrication lines | Early, with small demonstrated systems |
Wiring density is the clearest constraint on the superconducting path. Every physical qubit needs control and readout lines running from room-temperature electronics down into the millikelvin stage, and the cable count grows with the qubit count while the cooling budget of a dilution refrigerator does not. Scaling that approach linearly runs into physical limits well before a CRQC.
We read the table by function rather than by vendor. Fast gates favour superconducting circuits. Long-term storage with minimal error accumulation favours trapped ions or rare-earth systems. Massively parallel operations with flexible connectivity favour neutral atoms. Moving a quantum state between two locations favours photons. These are specialists, and asking any one of them to cover the whole workload means engineering compromises at every point.
What an assembled machine looks like
We decompose a large fault-tolerant computation into its functions, then assign each function to the technology suited to it.
Compute cores. Universal fault-tolerant logic runs on the fastest available modality, currently superconducting circuits with microsecond QEC cycles. The cores don’t need to be individually large. Several small ones can work in parallel on different parts of the algorithm.
Tiered quantum memory. Most qubits in a factoring run sit idle for the large majority of logical clock cycles, waiting on operations elsewhere. Holding them in fast, expensive, high-error-rate compute hardware wastes the scarcest resource in the machine. A memory tier built from long-coherence qubits stores idle states at lower error rates and lower cost per qubit. Rare-earth-doped crystals have shown coherence measured in hours in the laboratory. The design pattern is the L1, L2 and L3 cache hierarchy, transposed.
State factories. Error correction cannot supply certain gates directly, so the machine manufactures the resource states those gates consume, a process called magic state distillation. It’s one of the dominant overheads in fault-tolerant computing, and it’s separable. Dedicated modules can produce purified states and deliver them to the cores on demand.
Photonic interconnect. Modules exchange quantum states over a bus built from Bell pairs, two entangled qubits shared across a link and consumed to teleport a state from one end to the other. Photonics is the obvious carrier, for the same reason optical links carry traffic between racks today.
Classical HPC. Real-time decoders, syndrome processors and schedulers run on conventional high-performance hardware coupled tightly to the quantum modules. Syndrome data is the stream of error-detection measurements the decoder turns into corrections, and at CRQC scale that stream is large enough to strain the fastest classical systems available.
The orchestration problem
An assembled machine has to decide, continuously, what goes where.
- Which states stay in a compute core and which move to memory
- Which memory tier suits a given idle duration
- When to pre-fetch a state so a core isn’t left waiting
- When the cost of moving a state exceeds the cost of letting it accumulate errors in place
Those decisions repeat every QEC cycle, across thousands or millions of states, against a cost function that balances error accumulation, transfer latency, memory capacity, factory throughput and algorithmic dependencies at once. Hand-written heuristics tend to lose to learned schedulers on problems shaped like that, and a learned scheduler trained offline in simulation could run inference inside a microsecond control loop on specialised hardware.
Nobody has built one. Whether simulation-trained policies transfer to real hardware is unknown, and so is whether the optimisation surface is tractable at scale. In every other domain where heterogeneous computing arrived, though, the orchestration layer became the hardest and most valuable part of the stack.
What’s still missing
Fault-tolerant processors don’t exist at useful scale. Quantum memory has never been integrated with a superconducting processor, and the interface between millikelvin hardware and memory running at different temperatures is unsolved. Teleportation between modules has been demonstrated, but at fidelities and rates far below what a multi-module machine needs. The orchestration layer is hypothetical. Classical decoding at scale is a major programme in its own right.
We don’t know any of these to be impossible. All of them are hard, and integrating them is harder than any one of them.
What changes for threat assessment
Monitoring one platform under-reads the field. The question we would ask instead is which modalities combine well and how fast the integration problems yield. A programme that tracks superconducting qubit counts alone will miss a memory or interconnect result that shortens the timeline.
Progress becomes lumpier. In a single-modality model, one technology has to solve every problem. In an assembled model, an advance anywhere feeds the whole system. That widens the range of plausible dates and fattens the early tail.
The million-qubit reassurance has already expired. In 2019, Gidney and Ekerå estimated roughly 20 million noisy physical qubits to factor RSA-2048 in about eight hours. Gidney’s 2025 estimate put it below 1 million physical qubits in under a week, driven by algorithmic and error-correction improvements rather than by better hardware. Architecture is the next lever on the same number. Migration plans resting on “nobody has a million qubits” rest on a figure that moved twenty-fold in six years.
We treat integration capability as the variable to watch. The organisation that first assembles a working system may not hold the best qubits. It may hold the best interface engineering, the best interconnect, and the best scheduling software. Qubit-count league tables don’t measure any of that.
We expect the machine that eventually breaks deployed cryptography to be a system rather than a chip: distributed, specialised, orchestrated in software, and built from parts no single team invented.
We built Quantum Academy’s CQSI systems-integration program for architects who need to reason about these systems end to end – modality trade-offs, interconnect, control stacks and integration risk. For the migration side of the same problem, the methodology at pqcframework.org covers inventory, crypto-agility and sequencing, and PostQuantum.com carries the deeper technical analysis behind the resource estimates cited above.