NISQ, FTQC, FASQ: How to Read the Three Eras of Quantum Computing

Three numbers, from three different announcements, all describing quantum processors. IBM’s Condor chip carries 1,121 superconducting qubits. Google’s Willow chip carries 105. A Harvard and QuEra team reported 48 logical qubits built from roughly 280 neutral atoms. Ranked by the size of the integer, that is a clear ordering. Ranked by what the machines can reliably compute, the ordering is different, and the difference is not a detail of interpretation. The three results sit in different eras of the technology, and the field has three acronyms for those eras: NISQ, FTQC, and FASQ.

In the CQTP curriculum we treat NISQ, FTQC, and FASQ as the first vocabulary problem, because those three words determine what a qubit count means. A number without its era attached carries almost no information.

What Each Acronym Actually Claims

NISQ: Noisy Intermediate-Scale Quantum

John Preskill, a theoretical physicist at Caltech, coined NISQ in a 2018 paper describing the machines the field was about to get. “Intermediate-scale” meant processors of tens to hundreds of qubits, large enough that simulating them on a classical computer becomes hard. “Noisy” meant the qubits are unprotected. Every gate operation has some probability of corrupting the state, errors accumulate as the circuit gets deeper, and nothing in the machine detects or repairs them.

That’s the regime almost every quantum processor in commercial service still occupies. NISQ devices have produced genuine scientific results and at least one demonstration that classical simulation struggled to reproduce. What they have not produced is a commercially relevant problem solved faster or cheaper than a classical computer solves it. Preskill’s naming was partly an act of expectation management, and it has held up.

FTQC: Fault-Tolerant Quantum Computing

FTQC has no single coiner. It comes out of theoretical work in the mid-1990s, when Peter Shor, Andrew Steane and others constructed the first quantum error-correcting codes and proved the threshold theorem: if physical error rates fall below a certain level, arbitrarily long computations become possible by spending extra qubits on redundancy.

A fault-tolerant machine detects and repairs its own errors during the computation. It does this by encoding information across many physical qubits, so that a single component failure changes something measurable without destroying the encoded state. The point of the exercise is a logical error rate far below the physical one, low enough that a circuit of a billion operations still returns the right answer.

FTQC is now a present-day laboratory result at very small scale, and vendor claims about it have started arriving.

FASQ: Fault-Tolerant Application-Scale Quantum

Preskill introduced FASQ in a keynote at Q2B in late 2024, crediting Andrew Landahl with the acronym. It names the endpoint: machines that are error-corrected and also large enough to run a broad range of useful applications, rather than one carefully chosen demonstration.

No FASQ machine exists. None is close. The term is useful anyway, because it separates two things that marketing tends to fuse. A fault-tolerant processor with a dozen logical qubits is a real scientific achievement and cannot run a commercially interesting chemistry simulation. Application scale is a separate axis from fault tolerance, and both have to be crossed.

Preskill himself has suggested the field might do better to count operations rather than eras, proposing “megaquop” for a machine capable of a million reliable quantum operations. That framing has the advantage of being a measurement rather than a category.

Mitigation Is Not Correction

The single most common confusion in NISQ-era reporting is the gap between error mitigation and error correction. They sound like variations on one idea. They are not.

Error mitigation is post-processing. The circuit runs on noisy hardware, produces a noisy answer, and classical software estimates what the answer would have been on cleaner hardware. Zero-noise extrapolation is the best-known technique: run the same circuit several times with noise deliberately amplified, then extrapolate the trend back toward an imaginary zero-noise point. Probabilistic error cancellation is another, characterising the noise well enough to subtract its effect statistically.

These methods work, and they have extended what NISQ machines can do considerably. IBM’s 2023 experiment on its 127-qubit Eagle processor used mitigation to extract a credible physics result from circuits far deeper than the raw hardware should have supported. Mitigation will stay useful well into the fault-tolerant era as a supplement.

It doesn’t scale. The number of circuit repetitions needed grows exponentially with circuit depth, so a modest increase in the size of the problem produces an impossible increase in runtime. Mitigation buys a fixed amount of depth at rapidly rising cost, and then stops.

Error correction is different in kind. The machine measures error information while the computation runs and applies fixes in real time, without ever measuring the encoded data itself. That measurement is the trick, and it is the reason the threshold theorem exists. Below the threshold error rate, adding redundancy makes the encoded qubit better. Above it, adding redundancy makes things worse, since each extra component is another thing that can fail.

Google’s December 2024 Nature paper is the clearest published evidence that a superconducting device has crossed that line. Running surface codes at three sizes on the 105-qubit Willow chip, the team found that each two-step increase in code size cut the logical error rate by roughly a factor of two, and the encoded qubit outlived the best physical qubit on the chip. That’s the behaviour the theory predicts below threshold, observed rather than assumed.

The Arithmetic of Overhead

Apologies in advance, this next part is arithmetic, and it is the part that decides how every roadmap after it should be read.

A physical qubit is a piece of hardware: a superconducting circuit on a chip, an ion held in an electromagnetic trap, an atom pinned by a focused laser beam. A logical qubit is an encoding spread across many physical qubits, arranged so that failures in the components can be located and repaired without reading the encoded information.

The surface code is the workhorse encoding for most hardware. It arranges qubits in a two-dimensional grid and tolerates relatively high physical error rates, around one percent, which is why it became the default target. Its size is described by the code distance, an odd number counting how many single-qubit errors it takes to corrupt the encoded state undetectably. Distance 3 catches one error. Distance 7 catches three.

The grid holds two kinds of qubit. Data qubits carry the encoded state. Ancilla qubits sit between them and get measured repeatedly, every cycle, throughout the computation. Those repeated measurements are called syndrome measurements, and they report where an error occurred without revealing the encoded value. Classical decoding software then works out what correction to apply, and it has to do this faster than new errors arrive.

Now the cost. At a physical two-qubit gate error rate near one in a thousand, a surface-code logical qubit reliable enough for a long algorithm needs on the order of a thousand physical qubits. A few hundred of those are data qubits, the rest are ancillas and the extra machinery for performing logical operations between encoded qubits.

Scale that up. A thousand logical qubits at that ratio is roughly a million physical qubits, which is why cryptographically relevant quantum computing has been described in those terms for years. Craig Gidney and Martin Ekerå estimated in 2019 that factoring RSA-2048 would take about 20 million noisy qubits and eight hours. Gidney’s 2025 revision brought that under one million qubits for a run of under a week, on the strength of algorithmic and code improvements rather than better hardware. A twenty-fold reduction is significant progress and still leaves a gap of three orders of magnitude against the largest processors built.

Overhead is not only spatial. Every logical operation decomposes into many physical cycles, some of them strictly sequential. A machine can have enough qubits and still be too slow, so gate speed, measurement speed, qubit reset time and decoder latency all enter the calculation. This is one reason the fastest hardware and the most accurate hardware are not obviously the same bet.

The closest classical parallel is error-correcting memory. Early computers stored data in components that flipped bits at rates no modern engineer would accept, and the answer was redundancy: store each byte across more bits than the byte needs, use the extra bits to detect and repair corruption, and accept that a reliable byte costs several unreliable ones. Quantum error correction is that trade at an extreme ratio, a thousand unreliable components for one reliable one, and the industry is at the point where the first reliable bytes have been demonstrated. Classical computing took decades to get from that point to reliable memory at commodity scale.

Better Codes, Not Just More Qubits

The thousand-to-one ratio is a property of the surface code, not a law of nature. A second line of work attacks the overhead directly.

Quantum low-density parity-check codes, usually written qLDPC, encode information using check operations that each touch only a few qubits, in patterns that doesn’t have to be a flat grid. Some families encode many logical qubits in one block rather than one, which is where the efficiency comes from. IBM published a bivariate bicycle code that encodes 12 logical qubits in 288 physical qubits, roughly an order of magnitude better than the surface code at comparable protection.

The catch is connectivity. These codes need qubits to interact with partners that are not physically adjacent, which is easy for trapped ions and hard for a two-dimensional superconducting grid. Decoding them is also harder, and decoding has to run in real time.

Other approaches attack the same ratio from the hardware side. Biased-noise qubits suppress one error type by design, letting a code spend its redundancy on the errors that remain. Erasure conversion engineers the hardware so that failures announce their own location, and a known location is far cheaper to correct than an unknown one.

None of these approaches removes the need for redundancy. They lower the ratio: IBM’s bicycle code spends 24 physical qubits per logical qubit where the surface code spends a thousand, and that ratio is what a fabrication plan has to hit.

Not Every “Logical Qubit” Means the Same Thing

Return to the 48 logical qubits from 280 atoms mentioned at the top. Set against a ratio of a thousand physical qubits per logical qubit, that number looks impossible. It’s not fraudulent, and it’s not comparable.

The Harvard and QuEra work used small codes and error detection with post-selection: run the circuit, check whether an error was flagged, and discard the runs that were. Post-selection throws away most of the data and it can’t be used inside an algorithm that has to produce an answer on demand. Google’s Willow result used a much larger code on a single logical qubit, with correction applied during the run rather than filtered afterwards. Both are real. They measure different things.

So when a logical qubit count appears in an announcement, we ask four questions:

1. Is it correction or detection? Detection with post-selection is a stepping stone. Real-time correction with a decoder running inside the cycle budget is the thing algorithms need.
2. What is the logical error rate, and per what? Per cycle, per gate, and per algorithm are different denominators. A logical qubit that survives storage says nothing about logical gates between two of them.
3. Is it below threshold, and shown how? The demonstration is a series of increasing code distances with error rates falling at each step. A single code size proves the code was implemented, not that it scales.
4. What is the physical-to-logical ratio? Divide. If the answer is not in the hundreds, the encoding is doing less protective work than a surface code of the same name would.

Announced and demonstrated are also different words, and vendor roadmaps use both. A roadmap entry for 2030 is a plan, and plans in this field have moved before.

Where the Hardware Sits Today

Three platforms carry most of the commercial effort, and they have genuinely different strengths. There’s no consensus winner, and betting on one is a live commercial risk rather than a settled question.

Superconducting circuits

Aluminium or niobium circuits patterned on a chip, cooled to around ten millikelvin, behaving as artificial atoms. The standard design is the transmon, an oscillator engineered with uneven energy spacing so that two of its levels can be addressed as a qubit and the rest ignored. IBM, Google and Rigetti build on this platform.

The advantages are speed and fabrication. Two-qubit gates take tens of nanoseconds, error-correction cycles run at roughly a microsecond, and the devices are made with lithography borrowed from semiconductor manufacturing. Best-in-class two-qubit gate fidelity sits near 99.9 percent.

The costs are wiring, cooling and connectivity. Each qubit needs control lines entering a dilution refrigerator, qubits mostly talk to their immediate neighbours, and manufacturing variation means no two are quite identical. Scaling past a few thousand on one chip pushes the field toward modular designs with chips linked together.

Trapped ions

Individual charged atoms, ytterbium or calcium, suspended above a chip by electromagnetic fields, with the qubit encoded in two internal energy levels. IonQ and Quantinuum lead the commercial effort.

Ions are identical to each other by physics rather than by manufacturing tolerance, and they hold coherence for seconds. Two-qubit gate fidelities around 99.7 to 99.8 percent have been reported on Quantinuum’s H-series. Ions in a shared trap also interact all-to-all through their common motion, so a circuit does not have to be padded with swap operations to bring distant qubits together. That property is worth a great deal for qLDPC codes.

The constraint is throughput. Two-qubit gates take tens of microseconds, three orders of magnitude slower than superconducting gates, and scaling past a hundred ions in one trap requires physically shuttling ions between zones or linking separate traps with photons. The apparatus needs ultra-high vacuum and precisely stabilised lasers rather than a refrigerator, which trades one hard engineering problem for another.

Neutral atoms in optical tweezers

Uncharged atoms, typically rubidium, held in arrays of tightly focused laser beams. Gates are performed by exciting atoms into Rydberg states, orbitals so large that the atoms behave as strong electric dipoles and interact with their neighbours. QuEra and Pasqal are the visible commercial names.

Two properties make this platform interesting. Array sizes have grown very fast, into the thousands of atoms, and the tweezers can move atoms during a computation, so the connectivity pattern is reconfigurable rather than fixed at fabrication. Gate times fall between ions and superconductors, in the hundreds of nanoseconds.

Fidelities are the open question, with two-qubit gate errors around half a percent in leading experiments, and atoms are lost from the array and have to be reloaded. If the fidelity gap closes, the combination of atom count and reconfigurable connectivity is a strong position.

The other routes

Photonic quantum computing encodes qubits in light, which does not decohere the way matter does, and pays for it with probabilistic gate operations and demanding detector requirements. PsiQuantum has announced utility-scale photonic sites built around silicon manufacturing. Semiconductor spin qubits use electrons confined in silicon quantum dots, small and fast and potentially manufacturable on existing lines, currently demonstrated at small qubit counts. Topological qubits promise error resistance built into the physics; Microsoft’s 2025 announcement of a topological device drew substantial technical dispute, and the claim is not settled.

Hybrid architectures may end up mattering more than any single modality. Superconducting modules joined by photonic links, or ion traps networked the same way, would combine local gate speed with the connectivity that large codes want.

Algorithms Change When the Era Changes

The hardware story has an algorithmic twin, and it changes the same way.

NISQ-era algorithms are heuristics designed around shallow circuits and few qubits. The Variational Quantum Eigensolver and the Quantum Approximate Optimization Algorithm both split the work between a short quantum circuit and a classical optimiser that adjusts its parameters. They have produced interesting small-scale chemistry and physics results. They come with no proof of advantage, and classical algorithms have repeatedly caught up with the specific problems they targeted.

Fault-tolerant algorithms are a different family. Shor’s factoring algorithm, quantum phase estimation for chemistry, and Grover-based search subroutines all have provable scaling arguments behind them. They also require circuit depths that noisy hardware cannot survive, which is the whole reason the field is spending a thousand physical qubits per logical one.

There is a cost structure inside fault tolerance that shapes algorithm design. Codes handle one family of operations, the Clifford gates, almost for free. Everything else, the non-Clifford gates that give quantum computing its power, requires magic states: specially prepared resource states, distilled through a process that consumes many imperfect copies to produce one good one. Magic state distillation dominates the runtime of most serious fault-tolerant algorithms. So the practical question in algorithm design has become how to get the same answer with fewer non-Clifford operations.

This is why a distinct body of work now targets the early fault-tolerant regime: a few dozen to a few hundred logical qubits, not millions. Those algorithms trade circuit depth against qubit count, compile carefully to surface-code geometry, and push as much work as possible onto classical hardware. The discipline resembles programming for early classical machines with severe memory limits, and it is a skill the field is relearning.

Reading a Roadmap Without Being Sold

The eras will overlap for years. The working position we teach:

Treat physical qubit counts as capacity, not capability. A chip with 1,000 physical qubits and no error correction is a NISQ device, whatever the headline says.

Ask what a logical qubit claim was measured against. Correction or detection, real-time or post-selected, memory or gates.

Watch error rates more closely than qubit counts. Fidelity improvements compound through the error-correction ratio. A tenfold reduction in physical error rate cuts the overhead per logical qubit substantially, so it moves timelines more than a bigger chip does.

Separate fault tolerance from application scale. The first fault-tolerant machines will run small algorithms, not commercial workloads. Both crossings have to happen.

Discount modality certainty. Anyone who tells you the winning platform is already known is selling something. The market has not resolved this, and the honest position is that it won’t resolve soon.

The practical consequence for organisations is narrow and specific. Cryptographic migration timelines depend on FTQC arithmetic rather than NISQ demonstrations, and that arithmetic has been moving in one direction. Application planning in chemistry, materials and optimisation depends on FASQ, which remains distant and unscheduled. Confusing those two questions produces either premature investment or misplaced calm. Keeping FTQC arithmetic and FASQ status separate is what prevents both mistakes.

Learning This Properly

Reading a roadmap accurately takes more than three definitions. It takes enough of the underlying material to check the arithmetic yourself: how codes work, where overhead comes from, what a fidelity figure covers and what it excludes, and why the same word means different things on different hardware.

That’s the ground we cover in the CQTP program at Quantum Academy, in sequence, with the error-correction and benchmarking material worked through rather than summarised. For deeper technical treatment of the eras and the papers behind them, PostQuantum.com goes further into the primary literature.