Marin Ivezic
The Missing Kernel
One round of syndrome extraction on Google’s Willow processor takes about 1.1 microseconds. That number sets a deadline for everything above it. The decoder reading those syndromes has roughly a microsecond to return an answer, and if it takes longer, unprocessed rounds accumulate until the computation halts.
Engineers arriving from classical systems software go looking for the operating system that handles this, and find nothing that deserves the name. IBM’s Qiskit Runtime schedules jobs and applies error mitigation, on IBM hardware only. Riverlane builds real-time decoders and has narrowed its focus to decoding rather than system orchestration. Q-CTRL’s Fire Opal automates calibration as a middleware layer. Google, Amazon and Microsoft each run capable internal control stacks, none of which you can download, port, or point at someone else’s hardware. The field is in its mainframe era, vertically integrated and pre-standard.
The awkward part is that the hardware has already unbundled. You can buy a superconducting chip from one vendor, control electronics from another, a dilution refrigerator from a third, and a decoder from a fourth. Assembling those into a working machine is a systems integration job, and nobody has built the software layer that would make the assembly coherent.
Most treatments of this stack walk it bottom to top, from pulses up to cloud APIs. We prefer a different cut, because it matches how the engineering actually decomposes. Read the stack by deadline. Five timescales, each with its own failure mode, its own vendors, and its own body of prior art.
The framing borrows from hard real-time systems, and the borrowing is close enough to be useful. In an avionics or motor-control system a missed deadline produces a wrong answer rather than a slow one, which is why rate-monotonic analysis exists to prove in advance that the deadlines will be met. Quantum control has the same structure with a harsher penalty. A classical real-time system that misses a deadline serves stale data. A quantum system that misses one destroys the information it was holding, because there is no way to freeze a qubit and resume later.
The Nanosecond Band
The bottom of the stack is a hardware abstraction layer, or HAL: the software boundary that lets everything above it say “rotate qubit 4 about X by pi/2” without knowing what physical signal produces that rotation. The classical equivalent is a device driver. The quantum version is harder, because drivers for different platforms disagree about what a signal is.
What one gate means on three platforms
On a superconducting processor, a qubit is a transmon circuit with a transition frequency in the 4–8 GHz range, and an anharmonicity of roughly −300 MHz separating the computational transition from leakage into a second excited state. Room-temperature arbitrary waveform generators produce megahertz-bandwidth envelopes at gigasample rates, and those envelopes modulate a microwave carrier through an IQ mixer. The standard shaping technique is DRAG, derivative removal by adiabatic gate, in which the quadrature component of the pulse is proportional to the time derivative of the in-phase component. That relationship cancels spectral energy at the leakage frequency. Single-qubit gates run in tens of nanoseconds, and the signal travels down staged attenuators to a chip at 10–20 millikelvin before the readout comes back through a parametric amplifier.
On a trapped-ion processor, none of that applies. A ytterbium-171 hyperfine qubit is split by about 12.6 GHz, state preparation uses resonant light at 369.5 nm, and gates are driven by two off-resonant Raman beams whose frequency difference matches the qubit splitting. The optical wavelength gives micrometre spatial resolution, so individual ions can be addressed in a way that direct microwave drive cannot manage. In a QCCD architecture, quantum charge-coupled device, ions are physically transported between trap zones by DC electrodes updated at hundreds of kilohertz.
On a neutral-atom processor, individual rubidium or caesium atoms sit in optical tweezers, entangling gates use two-photon excitation to Rydberg states, and the blockade effect over a few micrometres prevents neighbouring atoms from being excited together. Before a circuit runs at all, the machine images the array, finds the vacancies, and physically rearranges atoms to fill them.
An abstraction covering all three has to expose more than a gate set. Ion transport and atom rearrangement are not gates. They have no analogue in a classical instruction set, they can fail, and they consume time from the same coherence budget the gates draw on.
The grammar underneath
The most mature attempt at a common pulse-level language is OpenPulse, the calibration grammar inside OpenQASM 3.0. It rests on three objects. A port is a hardware input or output endpoint. A frame binds a clock, a frequency and a phase into a stateful carrier. A waveform is a time-dependent envelope, with built-in shapes including Gaussian, constant and DRAG. The defcal construct then maps a gate on named physical qubits to a pulse sequence, play schedules an envelope on a frame, and barrier aligns frame clocks so that operations line up in time. Oxford Quantum Circuits accepts OpenQASM 3 with OpenPulse as a source language, so the specification is past the paper stage.
Prior art on the abstraction itself
Three efforts are worth studying before anyone starts a fourth.
Riverlane’s Quantum Hardware Abstraction Layer (QHAL), built under the UK’s NISQ.OS project, defined three abstraction levels and a minimum common instruction set spanning four qubit technologies, with a binary encoding meant for direct hardware consumption. The repository was archived and marked deprecated, and the company redirected its engineering into error correction.
QuTech’s QNodeOS, published in Nature in 2025, is the first operating system for quantum network nodes. It runs C++ on FreeRTOS on a Zynq system-on-chip, and it isolates every hardware dependency in one module called QDriver. Two implementations exist, one for trapped ions and one for nitrogen-vacancy centres. Porting the system to new hardware means reimplementing that single layer and nothing else.
The Quantum Device Management Interface from TU Munich takes the most pragmatic line of the three. It is a header-only C library that exposes a device’s qubit list, coupling map, supported gates, per-gate error rates and current calibration state through a key-value query interface, so a compiler can ask a machine what it is rather than being compiled against it.
The pattern across all three is consistent. Isolating hardware dependence inside one narrow module is an achievable piece of engineering. Persuading more than one vendor to adopt the same module is the part nobody has solved.
The Microsecond Band
Arithmetic of the backlog
A distance-d rotated surface code arranges d² data qubits and d²−1 ancilla qubits on a lattice. Every cycle, the ancillas measure parity checks called stabilizers, and each measurement outcome that flips is a syndrome, meaning evidence that an error occurred somewhere nearby. A decoder takes the stream of syndromes and infers which correction to apply. Each cycle consists of an ancilla reset, four layers of CNOT gates ordered carefully to avoid correlated errors, and an ancilla measurement, which is the slowest step at several hundred nanoseconds.
Google’s Willow experiment ran a distance-7 code on 101 qubits at about 1.1 microseconds per cycle, with a logical error rate near 0.143 per cent per cycle and an error suppression factor of roughly 2.14 for each two units of code distance. The logical qubit outlived the best physical qubit on the chip by a factor of about 2.4. That is the first time the trade has gone the right way on hardware.
Now the arithmetic that governs the software. Syndromes arrive at about 1 MHz, so the decoder’s budget is one microsecond per round. Suppose it averages 1.2 microseconds. Each round adds 200 nanoseconds of debt, and after a second of running the decoder is 200 milliseconds behind and falling further behind at a constant rate. It never recovers. Worse, latency is not free even when the decoder keeps up, because physical qubits keep accumulating errors while the correction is being computed, which raises the effective error rate the code has to absorb.
Google’s own real-time decoder averaged tens of microseconds of latency at distance 5, which the team identified as needing improvement. For scale at the other end, Gidney and Ekerå’s resource estimate for factoring RSA-2048 in eight hours assumes a reaction time on the order of 10 microseconds. Push that to 100 microseconds and the runtime stretches several-fold.
Three decoder families
Minimum-weight perfect matching, or MWPM, builds a graph in which each syndrome is a vertex and each edge is weighted by the negative log probability of the error chain connecting two syndromes, then finds the minimum-weight matching with Edmonds’ blossom algorithm. It sets the accuracy benchmark and tolerates circuit-level noise up to about one per cent. Its worst case is cubic, though sparse implementations exploit the fact that syndromes are rare at low error rates.
Union-Find grows clusters outward from each syndrome, merges them when they collide, and peels off a correction. It runs in almost linear time, one to two orders of magnitude faster than full matching, at a slightly lower threshold. That profile suits hardware implementation.
Machine-learning decoders such as DeepMind’s AlphaQubit use recurrent transformer architectures and beat matching on accuracy against real hardware data. They currently need GPU inference, which puts the round trip back into the latency budget.
Where the decoder runs
This is where the architecture gets decided, and the choice is a familiar one dressed in unfamiliar constraints.
Riverlane’s Collision Clustering decoder on an UltraScale+ FPGA reports under a microsecond per round at distance 23 with a small logic footprint, and its ASIC version in a 12 nm process occupies a fraction of a square millimetre at single-digit milliwatts. That power budget is the point: it can live inside the refrigerator at the 4 K stage, where roughly a watt of total cooling power is available. Yale’s Helios distributes decoding across several FPGAs in a tree topology to cover many logical qubits at once. NVIDIA’s DGX Quantum, paired with Quantum Machines control hardware, demonstrates a sub-4-microsecond round trip between QPU and GPU.
Put the decoder on a GPU and you buy accuracy and pay in round-trip latency across the interconnect. Put it in the fridge and you buy latency and pay in power, silicon area, and the loss of any ability to change the algorithm after tape-out.
The Millisecond Band
No pause, no resume
Circuit fidelity decays roughly as the product of the gate fidelities multiplied by an exponential in elapsed time over T2, the dephasing time. With T2 near 100 microseconds on a superconducting device and two-qubit gates in the tens of nanoseconds, that allows on the order of a couple of thousand sequential operations before the state is noise. Trapped ions and neutral atoms hold coherence for seconds, which changes the arithmetic but not the structure.
There is no swap-to-disk here. A quantum job cannot be checkpointed, suspended behind a higher-priority job, and resumed. Missing the coherence deadline doesn’t delay the result, it erases it, and the scheduler has to treat every job as a non-preemptible reservation.
Scheduling modes
IBM’s Qiskit Runtime shows what a first-generation quantum scheduler looks like. Job mode submits a single request into a shared queue. Batch mode groups independent jobs so they compile in parallel and run back to back. Session mode holds the processor exclusively and is not interrupted, not even for calibration, and it bills wall-clock time including the gaps when the classical side is thinking.
Those gaps are the reason the mode exists. A variational algorithm prepares a parameterised state, measures an expectation value over many shots, hands the result to a classical optimiser, gets new parameters back, and repeats. Small chemistry problems need hundreds of iterations and larger ones need far more, so every iteration that re-enters a shared queue costs more in waiting than in computing. Holding the machine also keeps the noise model stable, which keeps the error mitigation applied on top of it valid.
When the circuit doesn’t fit
Circuit cutting partitions a circuit too large for the available hardware into subcircuits, runs them separately, and reconstructs the result through a quasiprobability decomposition. The sampling overhead is exponential in the number of cuts, roughly a factor of four per cut wire and worse for cutting a two-qubit gate without classical communication between the fragments. It is expensive and it is sometimes the only route to an answer.
Dynamic circuits push in the opposite direction. Mid-circuit measurement with fast classical feedforward, now at the sub-microsecond scale on IBM hardware, allows conditional operations and qubit reuse through measure-and-reset. It also introduces non-deterministic delays, so the scheduler has to hold the idle qubits together with dynamical decoupling while the classical branch resolves.
The Compile-Time Band
Compilation runs off the critical path, with one caveat that shapes everything: it must finish while the calibration data it optimised against is still true.
Routing is NP-complete
Algorithms are written as though any qubit can interact with any other. Hardware has a fixed coupling graph. The compiler has to choose an initial placement of logical qubits onto physical ones, and then insert SWAP operations during execution to bring interacting qubits next to each other. Finding the mapping with minimum SWAP count is NP-complete, and the routing subproblem stays NP-hard even on a star graph.
Qiskit’s default router, SABRE, sweeps forward and backward through the circuit scoring candidate SWAPs against upcoming gates. It is stochastic, so the normal practice is to run a hundred trials and keep the best. Exact methods built on MaxSAT solvers produce substantially better circuits and want a compile budget measured in tens of minutes.
The SWAP tax
A SWAP decomposes into three CNOT gates, so at a one per cent CNOT error rate each SWAP costs about three per cent. Ten SWAPs leave you at 0.97 to the tenth, roughly 0.74. Fifty leave you at 0.22, and the circuit is no longer telling you anything.
That arithmetic is why topology is a software decision as much as a physics one. IBM’s heavy-hex lattice holds average connectivity near 2.67 neighbours per qubit, chosen deliberately to suppress frequency collisions and spectator errors during cross-resonance gates, and it pays for that in SWAP count. IBM’s move toward a square lattice with four-way connectivity is motivated explicitly by the compiler’s side of the ledger. Google’s grid uses tunable couplers. Trapped-ion machines offer all-to-all connectivity through shared vibrational modes and pay no SWAP tax at all, with much slower gates as the price.
Native gates and re-synthesis
Any two-qubit unitary can be built from at most three CNOTs, a result Vatan and Williams proved in 2004, but the cost depends on what the hardware natively does. IBM’s basis is CX with RZ, SX and X. Google’s includes a square-root-iSWAP, which covers most random two-qubit unitaries in two entangling gates rather than three. IonQ’s Mølmer–Sørensen interaction yields a CNOT with one entangling gate plus single-qubit corrections. Quantinuum’s parameterised ZZ gate collapses the common CNOT–RZ–CNOT pattern into a single native operation.
Qiskit’s transpiler moves a circuit through six stages, from decomposition and layout through routing, translation into the native basis, optimisation, and scheduling. The most productive optimisation is peephole re-synthesis, which collects a run of gates on the same pair of qubits, computes their combined unitary, and rebuilds it using the KAK decomposition, a canonical form that reveals the minimum entangling-gate count directly. Numerical synthesis tools such as BQSKit go further by fitting a parameterised circuit template to a target unitary with gradient-based optimisation, which finds solutions that rule-based rewriting cannot reach. IBM reports reductions of roughly 40 per cent in two-qubit gate count from reinforcement-learning passes trained on specific circuit classes.
The Hourly Band
What drifts
Everything the compiler optimised against is a snapshot with a short shelf life. Qubit frequencies wander by hundreds of kilohertz between calibrations. T1 and T2 fluctuate. Readout assignment matrices move, and crosstalk between neighbours changes with them. A hundred-qubit superconducting system is recalibrated on roughly a daily cycle, and the calibration is not a checklist but a dependency graph: resonator spectroscopy, then qubit spectroscopy, then Rabi amplitude, then Ramsey for fine frequency, then relaxation and echo measurements, then DRAG correction, then gate tuning, then benchmarking, then readout discrimination.
The underlying physics is unhelpful. Two-level-system defects in the oxides and interfaces of the chip couple to the qubit and drift in and out of resonance, producing low-frequency noise in the relaxation time itself. Google has also observed correlated multi-qubit error bursts consistent with cosmic-ray impacts, which no calibration schedule can anticipate.
Measuring a gate without measuring the readout
Randomized benchmarking is the standard instrument, and it is worth understanding why it is trusted. The procedure applies a sequence of m random Clifford gates, appends the single gate that inverts the whole sequence, and measures how often the qubit returns to its starting state. Averaging over the Clifford group turns an arbitrary error channel into simple depolarising noise, so the survival probability decays exponentially in m. State preparation and measurement errors, known collectively as SPAM, land in the fitted constants rather than the decay rate, which means the extracted gate error is clean of them. Interleaving a specific gate between the random ones gives a per-gate number. The single-qubit Clifford group has 24 elements and the two-qubit group has 11,520.
Continuous calibration
The direction of travel is away from scheduled downtime and toward a background service. Quantum Machines’ QUAlibrate expresses calibration as a directed graph of routines with conditional branching, so an orchestrator decides what to rerun based on what the last measurement returned, cutting multi-qubit calibration from hours to minutes. Sandia’s inline online calibration goes further and updates parameters after every individual shot, nudging rotation angles and two-qubit phases toward truth from the measurement outcomes themselves, and it can run on error-correction syndrome data without interrupting the computation.
Both point at the same design conclusion. Calibration belongs inside the kernel, running while jobs run, rather than in a maintenance window that invalidates the compiler’s assumptions the moment it ends.
Where the Bands Meet
Three problems cut across all five timescales, and they are the ones most likely to define the next generation of the stack.
Multi-tenancy. A 127-qubit processor running one small circuit at a time wastes most of itself. Research systems such as QuCloud+ partition the coupling graph into regions for concurrent programs and add inter-program SWAP mechanisms, while HyperQ bin-packs quantum virtual machines both spatially and temporally with buffer qubits left empty between them. Crosstalk is the shared-cache contention of this world, and the isolation guarantees are physical rather than logical.
Telemetry. Monitoring a quantum system means monitoring two machines at once. A dry dilution refrigerator has stages near 50 K, 4 K, several hundred millikelvin at the still, around 100 millikelvin at the cold plate, and 10–20 millikelvin at the mixing chamber, with sensors on temperature, gas-handling pressure, pulse-tube vibration and helium-3 circulation rate. Above that sit the quantum metrics, which drift on hourly timescales rather than the weekly and monthly rhythms of classical infrastructure. Cloud services expose almost none of this. Amazon Braket publishes task counts and end-to-end latency, and hardware parameters reach the user only through a device properties API, which is the standing tension between a clean cloud abstraction and hardware-aware optimisation.
Code choice. IBM’s bivariate bicycle codes, a family of quantum low-density parity-check codes published in Nature in 2024, encode 12 logical qubits into 288 physical qubits in the so-called gross code, roughly an order of magnitude better than the surface code at comparable distance. Every layer above changes as a result. Resources are allocated per code block rather than per logical qubit, the decoder must run belief propagation rather than graph matching, and the stabilizer checks are non-local, so the hardware needs long-range couplers that today’s lattices don’t have.
What to Take From This
The deadline hierarchy is the architecture. Sub-nanosecond pulse timing, microsecond decoding, millisecond coherence, hourly drift. Every design choice at one level constrains the level above it, and a stack that ignores the ordering will fail in the field rather than in simulation.
Hardware diversity isn’t converging. Microwave pulses, laser beams and optical tweezers have nothing in common at the signal level. The serious abstraction efforts accept that and isolate it in one module, as QNodeOS does with QDriver.
Latency is a budget, not an optimisation. The decision to put a decoder on an FPGA in the fridge, on a GPU across a PCIe link, or in a distributed tree is made once and constrains the system for its lifetime.
Calibration belongs in the runtime. Treating it as offline maintenance means the compiler is always optimising against a machine that no longer exists.
Nobody owns the middle. Vendors supply chips, control electronics, cryogenics and decoders. The layer that makes them one machine is currently written by hand, per site, per project.
That last point is where integration work actually lives right now, and it is skilled work. It requires reading a pulse specification and a decoder datasheet with equal fluency, sizing a latency budget before choosing a component, and knowing which of a vendor’s published numbers describe the system you are going to build rather than the demonstration they ran.
That is the ground our Certified Quantum Systems Integrator (CQSI) program covers, from control electronics and cryogenic constraints through compilation, error correction and orchestration. Current curriculum, prerequisites and enrollment details are at quantumacademy.com/. For deeper technical background on the layers described here, the extended treatment on PostQuantum.com goes further into each one.